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MOUNTAIN VIEW, Calif.----Sept. 18, 2000--Synopsys, Inc. (Nasdaq:SNPS) today announced that its Verilog Compiled Simulation (VCS) tool has enabled AMD to achieve a major milestone in regression throughput. AMD significantly shortened its verification time by achieving more than four billion simulation cycles per day. This performance was attained by running Synopsys' VCS(TM) Verilog simulator on a Linux-based server farm using the new AMD Athlon(TM) processors.

In addition, Synopsys and AMD have signed a multi-year, multi-million dollar volume purchase agreement to provide the VCS simulator to all of AMD's design communities. Based on the latest EDA Consortium reports, Synopsys believes that VCS is the No.1 Verilog simulator in terms of overall market share over the last four quarters.

Two key factors to AMD's decision were maximizing performance and minimizing risk, both essential for design verification. Combining VCS, the industry's fastest Verilog simulator, with the high-performance AMD Athlon microprocessor on a Linux server farm achieved the performance goals without the risk and expense of proprietary simulation acceleration hardware.

``VCS has already been used to verify our AMD Athlon processors, and is currently being utilized on the next generation Sledgehammer project,'' stated Fred Weber, vice president of engineering at AMD. ``Given VCS' strong track record and commitment to performance improvement, we will be well positioned to take advantage of a scalable high-performance verification platform that will enable future microprocessor development.''

``Verification is increasingly becoming the biggest bottleneck in complex IC designs,'' said Manoj Gandhi, senior vice president and general manager of the Verification Technology Group at Synopsys. ``The relentless pursuit of simulation performance that has made VCS the market leader, has enabled AMD to meet its demanding verification requirements. Our VCS simulator, running on Linux-based AMD Athlon processors, provides the highest possible regression throughput at the best price/performance point in the industry.''

Complete Functional Verification Solution

Synopsys provides a complete line of functional verification solutions supporting both Verilog and VHDL languages for complex IC designs. Synopsys' VCS Verilog simulator is the industry's benchmark for robust, high-performance RT and gate-level simulation for all design styles. Scirocco(TM), the next generation VHDL simulator, provides the industry's highest RT-Level performance and capacity for VHDL designs. In addition, Synopsys offers VERA(TM), a testbench automation tool for rapid generation of high functional coverage tests, and CoverMeter(TM), a comprehensive code coverage analysis tool for Verilog designs.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Synopsys is a registered trademark of Synopsys, Inc. VCS, CoverMeter, Sicrocco and VERA are all trademarks of Synopsys, Inc. AMD and AMD Athlon are registered trademarks of Advanced Micro Devices, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

     Synopsys, Inc.
     Catherine Glines-Dickson, 650/584-4170
     glines@synopsys.com
     or
     KVO Public Relations
     LeAnne Frank, 503/221-7403
     leanne_frank@kvo.com